1. Field of the Invention
The present invention is directed generally to smart-power technologies and more specifically to a method for manufacturing an insulating trench in a substrate for smart-power technologies.
2. Description of the Related Art
Smart-power technology is known as the monolithic integration of complex logic components with high-voltage power components in one substrate. Since the logic components are operated with voltage levels of about 5 volts, but voltages up to 500 volts occur at the high-voltage power components, an electrical separation of the high-voltage components from the logic components is required.
It is known to completely electrically insulate the high-voltage and low-voltage components from one another by dielectric insulation (see, for example, Yu Ohata et al, IEEE 1987 CICC, Pages 443-446). The components are thereby realized in a SOI substrate. A SOI substrate has an insulating layer of SiO.sub.2 on a single-crystal silicon wafer and a single-crystal silicon layer on the insulating layer. This single-crystal silicon layer is the surface of the SOI substrate. The insulating layer of the SOI substrate assures the vertical insulation, whereas the lateral insulation of the components is realized by trenches filled with insulating material. For many applications, the voltage behavior of the components is improved in that the sidewalls of the trenches are n.sup.+ or p.sup.+ doped over the entire depth down to the insulating layer of the SOI material before the trenches are filled with oxide (see N. Yasuhara et al, IEDM 1991, Pages 141-144).
For producing the lateral insulation, it is known to first implement the doping of the sidewalls after the etching of the trench. For example, this doping ensues by drive-out from doped glasses such as boron silicate glass (BSG) or phosphorous silicate glass (PSG), by occupation from the vapor phase or by ion implantation. The trench is subsequently filled with SiO.sub.2. For example, this occurs by thermal oxidation or by chemical vapor deposition (CVD) deposition of SiO.sub.2.
Since trench depths of about 20 .mu.m having aspect ratios (i.e., the quotient of trench depth to trench width) of 5-10 occur in smart-power technologies, it is problematical to produce a diffusion region having a uniform, prescribable expanse by ion implantation in the doping of the sidewalls. The ion implantation must be implemented angled, whereby the substrate must be turned four times in order to assure a somewhat uniform dopant concentration at all walls. Since doses of at least 5.times.10.sup.15 atoms/cm.sup.2 are necessary, this method is extremely time-consuming.
In the doping by drive-out from glasses or by occupation from the vapor phase, the layer of doped glass or the occupation layer must be in turn removed after the formation of the diffusion region in order to avoid an uncontrolled drive-out from these layers or a contamination of the equipment during the course of the further process execution. The layers used as doping sources must thereby be removed residue-free. Since these layers are SiO.sub.2 -like and are arranged directly on the insulating layer of the SOI substrate at the bottom of the trench, no etching stop is present at the bottom of the trench. During the residue-free removal of these layers, an attack on the insulating layer of the SOI substrate therefore occurs. When the trench is subsequently filled with SiO.sub.2 by thermal oxidation, the fact that the insulating layer has been incipiently etched or etched through leads to the formation of cavities that can no longer be filled. When the trench is filled using CVD SiO.sub.2, either an inadequate conformity of the deposition at atmospheric pressure or an extremely low deposition rate given low-pressure deposition must be accepted.